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page 1 of 11 document no. 70-0325-06 www.psemi.com ?2011-2012 peregrine semiconductor corp. all rights reserved. product description the pe64904 is a dune?-enhanced digitally tunable capacitor (dtc) based on peregrine?s ultracmos ? technology. dtc products provide a monolithically integrated impedance tuning solution for demanding rf applications. the pe64904 offers high rf power handling and ruggedness, while meeting challenging harmonic and linearity requirements. this highly versatile product can be used in series or shunt configurations to support a wide variety of tuning circuit topologies. the device is controlled through the widely supported 3-wire (spi compatible) interface. all decoding and biasing is integrated on-chip and no external bypassing or filtering components are required. peregrine?s dune? technology enables excellent linearity and exceptional harmonic performance. dune devices deliver performance superior to gaas devices with the economy and integration of conventional cmos. product specification ultracmos ? digitally tunable capacitor (dtc) 100 - 3000 mhz pe64904 features ?? 3-wire (spi compatible) serial interface with built-in bias voltage generation and esd protection ?? dune?-enhanced ultracmos ? device ?? 5-bit 32-state digitally tunable capacitor ?? series configuration c = 0.60 - 4.60 pf (7.7:1 tuning ratio) in discrete 129 ff steps ?? shunt configuration c = 1.14 - 5.10 pf (4.6:1 tuning ratio) in discrete 129 ff steps ?? high rf power handling (up to 38 dbm, 30 v pk rf) and high linearity ?? wide power supply range (2.3 to 3.6v) and low current consumption (typ. 140 a at 2.6v) ?? excellent 1.5 kv hbm esd tolerance on all pins ?? 2 x 2 x 0.45 mm qfn package ?? applications include: ?? tunable filter networks ?? tunable antennas ?? rfid ?? tunable matching networks ?? phase shifters ?? wireless communications figure 2. package type 10l 2 x 2 x 0.45 mm qfn package figure 1. functional block diagram 71-0066-01
product specification pe64904 page 2 of 11 ?2011-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0325-06 ultracmos ? rfic solutions table 1. electrical specifications @ 25c, v dd = 2.6v parameter configuration condition min typ max units operating frequency range both 100 3000 mhz minimum capacitance series shunt state = 00000, 100 mhz (rf+ to rf-) state = 00000, 100 mhz (rf+ to grounded rf-) 0.49 0.99 0.60 1.10 0.71 1.21 pf maximum capacitance series shunt state = 11111, 100 mhz (rf+ to rf-) state = 11111, 100 mhz (rf+ to grounded rf-) 4.09 4.59 4.60 5.10 5.11 5.61 pf parasitic capacitance series all states, 100 mhz (rf+ to gnd, rf- to gnd) 0.5 pf tuning ratio series shunt 100 mhz 100 mhz 7.7:1 4.6:1 step size both 5 bits (32 states), constant step size (100 mhz) 0.129 pf equivalent series resistance series state = 00000 state = 11111 1.40 1.33 ? quality factor (c min ) 1 shunt 100 mhz, with l s removed 1 ghz, with l s removed 2 ghz, with l s removed 3 ghz, with l s removed 10 35 32 25 quality factor (c max ) 1 shunt 100 mhz, with l s removed 1 ghz, with l s removed 2 ghz, with l s removed 3 ghz, with l s removed 27 25 11 6 self resonant frequency shunt state 00000 state 11111 7.5 3.1 ghz harmonics (2fo) 2 series 100 mhz - 3 ghz -36 dbm harmonics (3fo) 2 100 mhz - 3 ghz -36 dbm input intercept point (2nd order) series 100 mhz - 3 ghz, +18 dbm per tone, 1 mhz spacing 105 dbm input intercept point (3rd order) series 100 mhz - 3 ghz, +18 dbm per tone, 1 mhz spacing 65 dbm switching time 3, 4 both 50% ctrl to 10/90% delta capacitance between any two states 12 s start-up time 3 both time from v dd within specification to all performances within specification 100 s wake-up time 3, 4 both state change from standby mode to rf state to all perfor- mances within specification 100 s notes: 1. q for a shunt dtc based on a series rlc equivalent circuit. q = x c /r = (x-x l )/r, where x = x l +x c , x l = 2*pi*f*l, x c = -1/(2*pi*f*c), which is equal to remo ving the effect of par asitic inductance l s. 2. in series or shunt between 50 ? ports. pulsed rf input with 4620 s period, 50% duty cycle, measured per 3gpp ts 45.005. 3. dc path to ground at rf+ and rf- must be provided to achieve specified performance. 4. state change activated on falling edge of sen following data word.
product specification pe64904 page 3 of 11 document no. 70-0325-06 www.psemi.com ?2011-2012 peregrine semiconductor corp. all rights reserved. pin # pin name description 1 rf- negative rf port 1 2 rf- negative rf port 1 3 dgnd ground 4 v dd power supply pin 5 scl serial interface clock input 6 sen serial interface latch enable input 7 sda serial interface data input 8 rf+ positive rf port 1 9 rf+ positive rf port 1 10 gnd rf ground table 3. operating ranges figure 3. pin configuration (top view) table 2. pin descriptions exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. table 4. absolute maximum ratings symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any dc input -0.3 4.0 v v esd esd voltage (hbm, mil_std 883 method 3015.7) 1500 v electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. ? ? latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. moisture sensitivity level the moisture sensitivity level rating for the pe64904 in the 10-lead 2 x 2 x 0.45 mm qfn package is msl1. note 1: pins 1-2 and 8-9 must be ti ed together on pcb for optimal performance. parameter min typ max units v dd supply voltage 2.3 2.6 3.6 v i dd power supply current (v dd = 2.6v) 140 200 a v ih control voltage high 1.2 1.8 3.6 v v il control voltage low 0 0 0.57 v peak operating rf voltage 2 v p to v m v p to rfgnd v m to rfgnd 30 30 30 vpk vpk vpk t op operating temperature range -40 +85 c t st storage temperature range -65 +150 c i dd standby current (v dd = 2.6v) 25 a rf input power (50 ? ) 1 698 - 915 mhz 1710 -1910 mhz +34 +32 dbm dbm notes: 1. maximum power available from 50 ? source. pulsed rf input with 4620 s period, 50% duty cycle, measured per 3gpp ts 45.005. 2. node voltages defined per e quivalent circuit model schematic ( figure 18 ). when dtc is used as a part of reactive network, impedance transformation may cause the internal rf voltages (v p , v m ) to exceed peak operating rf voltage even with specified rf input power levels. for operation above about +20 dbm (100 mw), the complete rf circuit must be simulated using actual input power and load conditions, and internal node voltages (v p , v m in figure 18 ) monitored to not exceed 30 vpk.
product specification pe64904 page 4 of 11 ?2011-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0325-06 ultracmos ? rfic solutions figure 6. measured step size vs state (frequency) figure 5. measured shunt s 11 (major states) figure 7. measured series s 11 /s 22 (major states) performance plots @ 25c and 2.6v unless otherwise specified 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 capacitance (pf) frequency (ghz) c0 c1 c2 c4 c8 c16 c31 -262 -131 0 131 262 393 524 655 786 917 1048 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 step size (ff) state 100 mhz 1000 mhz 2000 mhz 2500 mhz -2 -1 0 1 2 3 4 5 6 7 8 9 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 02468101214161820222426283032 delta c (%), relative to c at +25c capacitance (pf) state measured shunt c vs. state (temperature) c (pf) at +85c c (pf) at +25c c (pf) at -40c delta c (%) at +85c delta c (%) at -40c figure 8. measured shunt c vs frequency (major states) figure 9. measured series s 21 vs frequency (major states) figure 4. measured shunt c (@ 100 mhz) vs state (temperature)
product specification pe64904 page 5 of 11 document no. 70-0325-06 www.psemi.com ?2011-2012 peregrine semiconductor corp. all rights reserved. figure 11. measured shunt q (state 0) vs frequency (temperature) 0 10 20 30 40 50 60 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 q frequency [ghz] q0 q1 q2 q4 q8 q16 q31 figure 10. measured shunt q vs frequency (major states) -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 0 10 20 30 40 50 60 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 delta q (%) relative to 25c q frequency (ghz) q (c31) at +85c q (c0) at -40c q (c0) at +25c delta q (%) at +85c delta q (%) at -40c figure 12. measured shunt q (state 31) vs frequency (temperature) -10 -5 0 5 10 15 20 25 30 35 40 45 50 0 10 20 30 40 50 60 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 delta q (%) relative to 25c q frequency (ghz) q (c0) at +85c q (c0) at +25c q (c0) at -40c delta q (%) at +85c delta q (%) at -40c q (c0) at +85c q (c0) at -40c q (c0) at +25c delta q (%) at +85c delta q (%) at -40c
product specification pe64904 page 6 of 11 ?2011-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0325-06 ultracmos ? rfic solutions operation at frequencies below 100 mhz the pe64904 may be operated below the 100 mhz specified minimum operating frequency. the total capacitance and peak operating rf voltage are de-rated down to 1 mhz. figure 13 shows the total shunt capacitance from 1 mhz through 100 mhz. as seen in figure 14 , the maximum rf voltage that can be placed across the rf terminals or across either rf terminal to ground is de-rated as a function of frequency. note: table 1 performance specifications are not guaranteed below 100 mhz. figures 13 , 14 , and 15 reflect performance of a typical pe64904. 0 5 10 15 20 25 30 35 0 102030405060708090100 quality factor frequency (mhz) c0 c1 c2 c4 c8 c16 c31 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 0 102030405060708090100 capacitance (pf) frequency (mhz) c0 c1 c2 c4 c8 c16 c31 figure 13. measured shunt c vs frequency (major states, 1 mhz - 100 mhz) figure 15. measured shunt q vs frequency (major states, 1 mhz - 100 mhz) 0 5 10 15 20 25 30 35 0 20406080100 vmax rf (v) frequency (mhz) figure 14. voltage derating vs frequency (1 mhz - 100 mhz)
product specification pe64904 page 7 of 11 document no. 70-0325-06 www.psemi.com ?2011-2012 peregrine semiconductor corp. all rights reserved. table 6. serial interface timing characteristics b4 b3 b2 b1 b0 d4 d3 d2 d1 d0 b5 stb 1 b7 b6 0 0 msb (first in) lsb (last in) table 5. register map serial interface operation and sharing the pe64904 is controlled by a three wire spi- compatible interface. as shown in figure 16 , the serial master initiates the start of a telegram by driving the sen (serial enable) line high. each bit of the 8-bit telegram is clocked in on the rising edge of the scl (serial clock) line. sda bits are clocked by most significant bit (msb) first, as shown in table 5 and figure 16 . transactions on sda (serial data) are allowed on the falling edge of scl. the dtc activates the data on the falling edge of sen. the dtc does not count how many bits are clocked and only maintains the last 8 bits it received. figure 17. recommended bus sharing scl sda v dd gnd dgnd rf- rf+ scl sda v dd sen gnd dgnd rf- rf+ scl sda v dd dtc 1 sen sen2 sen1 dtc 2 more than 1 dtc can be controlled by one interface by utilizing a dedicated enable (sen) line for each dtc. sda, scl, and v dd lines may be shared as shown in figure 17 . dedicated sen lines act as a chip select such that each dtc will only respo nd to serial transactions intended for them. this makes each dtc change states sequentially as they are programmed. alternatively, a dedicated sda line with common sen can be used. this allows all dtcs to change states simultaneously, but requires all dtcs to be programmed even if the state is not changed. figure 16. serial interface timing diagram (oscilloscope view) note 1: the dtc is active when low (set to 0) and in low-current stand-by mode when high (set to 1) b5 b6 t r t dhd t dsu 1/f clk b7 b0 b4 b3 b2 b1 d m-1 <7:0> d m <7:0> b0 d m-2 <7:0> t epw t f t esu t ehd sen scl sda dtc data v dd = 2.6v, -40c < t a < +85c, unless otherwise specified symbol parameter min max units f clk serial clock frequency 26 mhz t r scl, sda, sen rise time 6.5 ns t f scl, sda, sen fall time 6.5 ns t esu sen rising edge to scl rising edge 19.2 ns t ehd scl rising edge to sen falling edge 19.2 ns t dsu sda valid to scl rising edge 13.2 ns t dhd sda valid after scl rising edge 13.2 ns t eow sen falling edge to sen rising edge 38.4 ns
product specification pe64904 page 8 of 11 ?2011-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0325-06 ultracmos ? rfic solutions figure 18. equivalent circuit model schematic equivalent circuit model description the dtc equivalent circuit model includes all parasitic elements and is accurate in both series and shunt configurations, reflecting physical circuit behavior accurately and providing very close correlation to measured data. it can easily be used in circuit simulation programs. most parameters are state independent, and simple equations are provided for the state dependent parameters. the tuning core capacitance c s represents capacitance between rf+ and rf- ports. it is linearly proportional to state (0 to 31 in decimal) in a discrete fashion. the series tuning ratio is defined as c smax /c smin . c p represents the circuit and package parasitics from rf ports to gnd. in shunt configuration the total capacitance of the dtc is higher due to parallel combination of c p and c s . in series configuration, c s and c p do not add in parallel and the dtc appears as an impedance transformation network. parasitic inductance due to circuit and package is modeled as l s and causes the apparent capacitance of the dtc to increase with frequency until it reaches self resonant frequency (srf). the value of srf depends on state and is approximately inversely proportional to the square root of capacitance. the overall dissipative losses of the dtc are modeled by r s , r p1 and r p2 resistors. the parameter r s represents the equivalent series resistance (esr) of the tuning core and is dependent on state. r p1 and r p2 represent losses due to the parasitic and biasing networks, and are state-independent. table 8. equivalent circuit model parameters table 9. equivalent circuit data variable equation (state = 0, 1, 2?31) units c s 0.129*state + 0.600 pf r s 20/(state+20/(state+0.7)) + 0.7 ? r p1 7 ? r p2 10 k ? c p 0.5 pf l s 0.27 nh state dtc core binary decimal c s [pf] r s [ ? ] 00000 0 0.60 1.40 00001 1 0.73 2.27 00010 2 0.86 2.83 00011 3 0.99 3.08 00100 4 1.12 3.12 00101 5 1.25 3.05 00110 6 1.37 2.93 00111 7 1.50 2.78 01000 8 1.63 2.64 01001 9 1.76 2.51 01010 10 1.89 2.39 01011 11 2.02 2.27 01100 12 2.15 2.17 01101 13 2.28 2.08 01110 14 2.41 2.00 01111 15 2.54 1.93 10000 16 2.66 1.86 10001 17 2.79 1.80 10010 18 2.92 1.75 10011 19 3.05 1.70 10100 20 3.18 1.65 10101 21 3.31 1.61 10110 22 3.44 1.57 10111 23 3.57 1.54 11000 24 3.70 1.51 11001 25 3.83 1.48 11010 26 3.95 1.45 11011 27 4.08 1.42 11100 28 4.21 1.40 11101 29 4.34 1.37 11110 30 4.47 1.35 11111 31 4.60 1.33 table 7. maximum operating rf voltage condition limit v p to v m 30 vpk v p to rfgnd 30 vpk v m to rfgnd 30 vpk l s l s r s c s c p c p r p1 r p1 r p2 r p2 rf- rf+ rfgnd v p v m
product specification pe64904 page 9 of 11 document no. 70-0325-06 www.psemi.com ?2011-2012 peregrine semiconductor corp. all rights reserved. figure 20. recommended layout of multiple dtcs figure 19. recommended schematic of multiple dtcs layout recommendations for optimal results, place a ground fill directly under the dtc package on the pcb. layout isolation is desired between all control and rf lines. when using the dtc in a shunt configuration, it is important to make sure the rf-pin is solidly grounded to a filled ground plane. ground traces should be as short as possible to minimize inductance. a continuous ground plane is preferred on the top layer of the pcb. when multiple dtcs are used together, the physical distance between them should be minimized and the connection should be as wide as possible to minimize series parasitic inductance. evaluation board the 101-0597 evaluation board (evb) was designed for accurate measurement of the dtc impedance and loss. two configurations are available: 1 port shunt (j3) and 2 port series (j4, j5). three calibration standards are provided. the open (j2) and short (j1) standards (104 ps delay) are used for performing port extensions and accounting for electrical length and transmission line loss. the thru (j9, j10) standard can be used to estimate pcb transmission line losses for scalar de-embedding of the 2 port series configuration (j4, j5). the board consists of a 4 layer stack with 2 outer layers made of rogers 4350b ( r = 3.48) and 2 inner layers of fr4 ( r = 4.80). the total thickness of this board is 62 mils (1.57 mm). the inner layers provide a ground plane for the transmission lines. each transmission line is designed using a coplanar waveguide with ground plane (cpwg) model using a trace width of 32 mils (0.813 mm), gap of 15 mils (0.381 mm), and a metal thickness of 1.4 mils (0.051 mm). figure 21. evaluation board layout 101-0597
product specification pe64904 page 10 of 11 ?2011-2012 peregrine semiconductor corp. all rights reserved. document no. 70-0325-06 ultracmos ? rfic solutions figure 23. marking specifications ppzz yww marking spec symbol package marking definition pp cg part number marking for pe64904 zz 00-99 last two digits of lot code y 0-9 last digit of year, starting from 2009 (0 for 2010, 1 for 2011, etc) ww 01-53 work week figure 22. package drawing 10-lead 2 x 2 x 0.45 mm 17-0112 19-2002
product specification pe64904 page 11 of 11 document no. 70-0325-06 www.psemi.com ?2011-2012 peregrine semiconductor corp. all rights reserved. order code package description shipping method pe64904mlbb-z 10-lead qfn 2 x 2 x 0.45 mm package part in tape and reel 3000 units/t&r EK64904-12 evaluation kit ev aluation kit 1 set/box figure 24. tape and reel specifications 10-lead 2 x 2 x 0.45 mm tape feed direction table 9. ordering information advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product developm ent. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for dam ages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. all other trademarks mentioned herein are the property of their respective companies. sales contact and information for sales and contact information please visit www.psemi.com .

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